Make files from

However, the cases where double-colon rules really make sense are those where the order of executing the recipes would not matter. Double-colon rules are somewhat obscure and not often very useful; they provide a mechanism for cases in which the method used to update a target differs depending on which prerequisite files caused the update, and such cases are rare.

Each double-colon rule should specify a recipe; if it does not, an implicit rule will be used if one applies. In the makefile for a program, many of the rules you need to write often say only that some object file depends on some header file. For example, if main. You need this rule so that make knows that it must remake main.

You can see that for a large program you would have to write dozens of such rules in your makefile. And, you must always be very careful to update the makefile every time you add or remove an include. To avoid this hassle, most modern C compilers can write these rules for you, by looking at the include lines in the source files. For example, the command:. Note that such a rule constitutes mentioning main. That command would create a file depend containing all the automatically-generated prerequisites; then the makefile could use include to read them in see Include.

In GNU make , the feature of remaking makefiles makes this practice obsolete—you need never tell make explicitly to regenerate the prerequisites, because it always regenerates any makefile that is out of date. See Remaking Makefiles. The practice we recommend for automatic prerequisite generation is to have one makefile corresponding to each source file. For each source file name. That way only the source files that have changed need to be rescanned to produce the new prerequisites.

Here is the pattern rule to generate a file of prerequisites i. See Pattern Rules , for information on defining pattern rules. This omits prerequisites on system header files. See Include. See Substitution Refs , for full information on substitution references. See How Make Works. The recipe of a rule consists of one or more shell command lines to be executed, one at a time, in the order they appear. Typically, the result of executing these commands is that the target of the rule is brought up to date.

See Recipe Execution. Makefiles have the unusual property that there are really two distinct syntaxes in one file. Most of the makefile uses make syntax see Writing Makefiles. However, recipes are meant to be interpreted by the shell and so they are written using shell syntax. The make program does not try to understand shell syntax: it performs only a very few specific translations on the content of the recipe before handing it to the shell.

Each line in the recipe must start with a tab or the first character in the value of the. Blank lines and lines of just comments may appear among the recipe lines; they are ignored. One of the few ways in which make does interpret recipes is checking for a backslash just before the newline. As in normal makefile syntax, a single logical recipe line can be split into multiple physical lines in the makefile by placing a backslash before each newline.

A sequence of lines like this is considered a single recipe line, and one instance of the shell will be invoked to run it. Both the backslash and the newline characters are preserved and passed to the shell. Whitespace is never added to the recipe. If you specify a different shell in your makefiles it may treat them differently. This is often the case when passing scripts to languages such as Perl, where extraneous backslashes inside the script can change its meaning or even be a syntax error.

One simple way of handling this is to place the quoted string, or even the entire command, into a make variable then use the variable in the recipe. If we rewrite our example above using this method:. If you like, you can also use target-specific variables see Target-specific Variable Values to obtain a tighter correspondence between the variable and the recipe that uses it.

The other way in which make processes recipes is by expanding any variable references in them see Basics of Variable References. This occurs after make has finished reading all the makefiles and the target is determined to be out of date; so, the recipes for targets which are not rebuilt are never expanded. Variable and function references in recipes have identical syntax and semantics to references elsewhere in the makefile. Normally make prints each line of the recipe before it is executed.

We call this echoing because it gives the appearance that you are typing the lines yourself. Typically you would use this for a command whose only effect is to print something, such as an echo command to indicate progress through the makefile:. See Summary of Options. This flag is useful for finding out which recipes make thinks are necessary without actually doing them.

A rule in the makefile for the special target. When it is time to execute recipes to update a target, they are executed by invoking a new sub-shell for each line of the recipe, unless the. Please note: this implies that setting shell variables and invoking shell commands such as cd that set a context local to each process will not affect the following lines in the recipe.

Then make will invoke one shell to run the entire line, and the shell will execute the statements in sequence. Sometimes you would prefer that all the lines in the recipe be passed to a single invocation of the shell.

There are generally two situations where this is useful: first, it can improve performance in makefiles where recipes consist of many command lines, by avoiding extra processes.

Second, you might want newlines to be included in your recipe command for example perhaps you are using a very different interpreter as your SHELL. ONESHELL special target appears anywhere in the makefile then all recipe lines for each target will be provided to a single invocation of the shell.

Newlines between recipe lines will be preserved. This feature is intended to allow existing makefiles to add the. Since the special prefix characters are not legal at the beginning of a line in a POSIX shell script this is not a loss in functionality. For example, this works as expected:. Even with this special feature, however, makefiles with. For example, normally if any line in the recipe fails, that causes the rule to fail and no more recipe lines are processed.

You can modify. Ultimately you may need to harden your recipe lines to allow them to work with. The argument s passed to the shell are taken from the variable. The default value of. This is because the SHELL environment variable is used to specify your personal choice of shell program for interactive use. It would be very bad for personal choices like this to affect the functioning of makefiles.

See Variables from the Environment. Furthermore, when you do set SHELL in your makefile that value is not exported in the environment to recipe lines that make invokes. You can override this behavior by explicitly exporting SHELL see Communicating Variables to a Sub- make , forcing it to be passed in the environment to recipe lines.

The stock shell, command. In every directory it examines, make will first look for the specific file sh in the example above. If this is not found, it will also look in that directory for that file with one of the known extensions which identify executable files. For example. If any of these attempts is successful, the value of SHELL will be set to the full pathname of the shell as found.

However, if none of these is found, the value of SHELL will not be changed, and thus the line that sets it will be effectively ignored. This is so make will only support features specific to a Unix-style shell if such a shell is actually installed on the system where make runs.

Note that this extended search for the shell is limited to the cases where SHELL is set from the Makefile; if it is set in the environment or command line, you are expected to set it to the full pathname of the shell, exactly as things are on Unix.

GNU make knows how to execute several recipes at once. Normally, make will execute only one recipe at a time, waiting for it to finish before executing the next. You can inhibit parallelism in a particular makefile with the. The default number of job slots is one, which means serial execution one thing at a time. Handling recursive make invocations raises issues for parallel execution.

For more information on this, see Communicating Options to a Sub- make. If a recipe fails is killed by a signal or exits with a nonzero status , and errors are not ignored for that recipe see Errors in Recipes , the remaining recipe lines to remake the same target will not be run.

If make terminates for any reason including a signal with child processes running, it waits for them to finish before actually exiting. When the system is heavily loaded, you will probably want to run fewer jobs than when it is lightly loaded. When running several recipes in parallel the output from each recipe appears as soon as it is generated, with the result that messages from different recipes may be interspersed, sometimes even appearing on the same line.

This can make reading the output very difficult. This option instructs make to save the output from the commands it invokes and print it all once the commands are completed.

Additionally, if there are multiple recursive make invocations running in parallel, they will communicate so that only one of them is generating output at a time. There are four levels of granularity when synchronizing output, specified by giving an argument to the option e. This is the default: all output is sent directly as it is generated and no synchronization is performed.

Output from each individual line of the recipe is grouped and printed as soon as that line is complete. If a recipe consists of multiple lines, they may be interspersed with lines from other recipes. Output from the entire recipe for each target is grouped and printed once the target is complete. This is the default if the --output-sync or -O option is given with no argument.

Output from each recursive invocation of make is grouped and printed once the recursive invocation is complete.

Regardless of the mode chosen, the total build time will be the same. The only difference is in how the output appears. The difference between them is in how recipes that contain recursive invocations of make are treated see Recursive Use of make. This ensures output from all the targets built by a given recursive make instance are grouped together, which may make the output easier to understand.

However it also leads to long periods of time during the build where no output is seen, followed by large bursts of output. If you are not watching the build as it proceeds, but instead viewing a log of the build after the fact, this may be the best option for you. If you are watching the output, the long gaps of quiet during the build can be frustrating.

The recursive make will perform the synchronization for its targets and the output from each will be displayed immediately when it completes. Be aware that output from recursive lines of the recipe are not synchronized for example if the recursive line prints a message before running make , that message will not be synchronized.

For example, many programs that can display colorized output will not do so if they determine they are not writing to a terminal. Two processes cannot both take input from the same device at the same time. To make sure that only one recipe tries to take input from the terminal at once, make will invalidate the standard input streams of all but one running recipe. It is unpredictable which recipe will have a valid standard input stream which will come from the terminal, or wherever you redirect the standard input of make.

The first recipe run will always get it first, and the first recipe started after that one finishes will get it next, and so on. We will change how this aspect of make works if we find a better alternative. In the mean time, you should not rely on any recipe using standard input at all if you are using the parallel execution feature; but if you are not using this feature, then standard input works normally in all recipes.

After each shell invocation returns, make looks at its exit status. If the shell completed successfully the exit status is zero , the next line in the recipe is executed in a new shell; after the last line is finished, the rule is finished.

If there is an error the exit status is nonzero , make gives up on the current rule, and perhaps on all rules. Sometimes the failure of a certain recipe line does not indicate a problem. For example, you may use the mkdir command to ensure that a directory exists.

If the directory already exists, mkdir will report an error, but you probably want make to continue regardless. This is less flexible but sometimes useful. When an error happens that make has not been told to ignore, it implies that the current target cannot be correctly remade, and neither can any other that depends on it either directly or indirectly.

No further recipes will be executed for these targets, since their preconditions have not been achieved. Normally make gives up immediately in this circumstance, returning a nonzero status. The usual behavior assumes that your purpose is to get the specified targets up to date; once make learns that this is impossible, it might as well report the failure immediately.

Usually when a recipe line fails, if it has changed the target file at all, the file is corrupted and cannot be used—or at least it is not completely updated. The situation is just the same as when the shell is killed by a signal; see Interrupts.

So generally the right thing to do is to delete the target file if the recipe fails after beginning to change the file. This is almost always what you want make to do, but it is not historical practice; so for compatibility, you must explicitly request it.

If make gets a fatal signal while a shell is executing, it may delete the target file that the recipe was supposed to update. The purpose of deleting the target is to make sure that it is remade from scratch when make is next run. Why is this? Suppose you type Ctrl-c while a compiler is running, and it has begun to write an object file foo.

The Ctrl-c kills the compiler, resulting in an incomplete file whose last-modification time is newer than the source file foo. But make also receives the Ctrl-c signal and deletes this incomplete file. If make did not do this, the next invocation of make would think that foo. You can prevent the deletion of a target file in this way by making the special target. Before remaking a target, make checks to see whether it appears on the prerequisites of. Some reasons why you might do this are that the target is updated in some atomic fashion, or exists only to record a modification-time its contents do not matter , or must exist at all times to prevent other sorts of trouble.

Although make does its best to clean up there are certain situations in which cleanup is impossible. For example, make may be killed by an uncatchable signal. Or, one of the programs make invokes may be killed or crash, leaving behind an up-to-date but corrupt target file: make will not realize that this failure requires the target to be cleaned.

Or make itself may encounter a bug and crash. Most commonly these recipes create temporary files rather than updating the target directly, then rename the temporary file to the final target name. Recursive use of make means using make as a command in a makefile.

This technique is useful when you want separate makefiles for various subsystems that compose a larger system. You can do it by writing this:. You can write recursive make commands just by copying this example, but there are many things to know about how they work and why, and about how the sub- make relates to the top-level make. This value is never touched by make again: in particular note that if you include files from other directories the value of CURDIR does not change. The value has the same precedence it would have if it were set in the makefile by default, an environment variable CURDIR will not override this value.

Note that setting this variable has no impact on the operation of make it does not cause make to change its working directory, for example. The value of this variable is the file name with which make was invoked. If you use a special version of make to run the top-level makefile, the same special version will be executed for recursive invocations. See Instead of Executing the Recipes.

This special feature is only enabled if the MAKE variable appears directly in the recipe: it does not apply if the MAKE variable is referenced through expansion of another variable. Recipe lines containing MAKE are executed normally despite the presence of a flag that causes most recipes not to be run. Variable values of the top-level make can be passed to the sub- make through the environment by explicit request.

To pass down, or export , a variable, make adds the variable and its value to the environment for running each line of the recipe. The sub- make , in turn, uses the environment to initialize its table of variable values.

Except by explicit request, make exports a variable only if it is either defined in the environment initially or set on the command line, and if its name consists only of letters, numbers, and underscores. Some shells cannot cope with environment variable names consisting of characters other than letters, numbers, and underscores.

See Choosing the Shell. Variables are not normally passed down if they were created by default by make see Variables Used by Implicit Rules. The sub- make will define these for itself. If you want to export specific variables to a sub- make , use the export directive, like this:. If you want to prevent a variable from being exported, use the unexport directive, like this:.

In both of these forms, the arguments to export and unexport are expanded, and so could be variables or functions which expand to a list of variable names to be un exported.

You may notice that the export and unexport directives work in make in the same way they work in the shell, sh. This tells make that variables which are not explicitly mentioned in an export or unexport directive should be exported.

Any variable given in an unexport directive will still not be exported. If you use export by itself to export variables by default, variables whose names contain characters other than alphanumerics and underscores will not be exported unless specifically mentioned in an export directive. The behavior elicited by an export directive by itself was the default in older versions of GNU make.

If your makefiles depend on this behavior and you want to be compatible with old versions of make , you can write a rule for the special target. This will be ignored by old make s, while the export directive will cause a syntax error. Likewise, you can use unexport by itself to tell make not to export variables by default.

Since this is the default behavior, you would only need to do this if export had been used by itself earlier in an included makefile, perhaps. You cannot use export and unexport by themselves to have variables exported for some recipes and not for others. The last export or unexport directive that appears by itself determines the behavior for the entire run of make. The incrementation happens when make sets up the environment for a recipe. This variable, if defined in the outer-level makefile, is passed down through the environment; then it serves as a list of extra makefiles for the sub- make to read before the usual or specified ones.

This variable is set up automatically by make to contain the flag letters that make received. In response, it takes the flags from that value and processes them as if they had been given as arguments. See Overriding Variables. This is not usually useful to do. You probably do not care about this. If you want your makefiles to be compatible with old make programs, use this technique; it will work fine with more modern make versions too.

That variable is set only for compatibility; make does not interpret a value you set for it in any way. If you do put MAKEFLAGS in your environment, you should be sure not to include any options that will drastically affect the actions of make and undermine the purpose of makefiles and of make itself. When the same sequence of commands is useful in making various targets, you can define it as a canned sequence with the define directive, and refer to the canned sequence from the recipes for those targets.

The canned sequence is actually a variable, so the name must not conflict with other variable names. Here run-yacc is the name of the variable being defined; endef marks the end of the definition; the lines in between are the commands.

See Defining Multi-Line Variables , for a complete explanation of define. The first command in this example runs Yacc on the first prerequisite of whichever rule uses the canned sequence.

The output file from Yacc is always named y. To use the canned sequence, substitute the variable into the recipe of a rule. You can substitute it like any other variable see Basics of Variable References. Because variables defined by define are recursively expanded variables, all the variable references you wrote inside the define are expanded now. This is a realistic example, but this particular one is not needed in practice because make has an implicit rule to figure out these commands based on the file names involved see Using Implicit Rules.

In recipe execution, each line of a canned sequence is treated just as if the line appeared on its own in the rule, preceded by a tab. In particular, make invokes a separate sub-shell for each line. For example, using this canned sequence:. But it will echo the following two recipe lines.

On the other hand, prefix characters on the recipe line that refers to a canned sequence apply to every line in the sequence. So the rule:. It is sometimes useful to define recipes which do nothing. This is done simply by giving a recipe that consists of nothing but whitespace. You could also use a line beginning with a recipe prefix character to define an empty recipe, but this would be confusing because such a line looks empty. You may be wondering why you would want to define a recipe that does nothing.

One reason this is useful is to prevent a target from getting implicit recipes from implicit rules or the. You may be inclined to define empty recipes for targets that are not actual files, but only exist so that their prerequisites can be remade. However, this is not the best way to do that, because the prerequisites may not be remade properly if the target file actually does exist. See Phony Targets , for a better way to do this.

These values are substituted by explicit request into targets, prerequisites, recipes, and other parts of the makefile. In some other versions of make , variables are called macros. Variables can represent lists of file names, options to pass to compilers, programs to run, directories to look in for source files, directories to write output in, or anything else you can imagine.

However, variable names containing characters other than letters, numbers, and underscores should be considered carefully, as in some shells they cannot be passed through the environment to a sub- make see Communicating Variables to a Sub- make.

Variable names are case-sensitive. It is traditional to use upper case letters in variable names, but we recommend using lower case letters for variable names that serve internal purposes in the makefile, and reserving upper case for parameters that control implicit rules or for parameters that the user should override with command options see Overriding Variables. A few variables have names that are a single punctuation character or just a few characters.

These are the automatic variables , and they have particular specialized uses. See Automatic Variables. Variable references can be used in any context: targets, prerequisites, recipes, most directives, and new variable values. Here is an example of a common case, where a variable holds the names of all the object files in a program:.

A dollar sign followed by a character other than a dollar sign, open-parenthesis or open-brace treats that single character as the variable name. However, this practice can lead to confusion e. One place where readability is often improved is automatic variables see Automatic Variables. There are two ways that a variable in GNU make can have a value; we call them the two flavors of variables. The two flavors are distinguished in how they are defined and in what they do when expanded.

The first flavor of variable is a recursively expanded variable. The value you specify is installed verbatim; if it contains references to other variables, these references are expanded whenever this variable is substituted in the course of expanding some other string.

When this happens, it is called recursive expansion. This flavor of variable is the only sort supported by most other versions of make. It has its advantages and its disadvantages. An advantage most would say is that:. A major disadvantage is that you cannot append something on the end of a variable, as in. Actually make detects the infinite loop and reports an error. Another disadvantage is that any functions see Functions for Transforming Text referenced in the definition will be executed every time the variable is expanded.

This makes make run slower; worse, it causes the wildcard and shell functions to give unpredictable results because you cannot easily control when they are called, or even how many times. To avoid all the problems and inconveniences of recursively expanded variables, there is another flavor: simply expanded variables. The value of a simply expanded variable is scanned once and for all, expanding any references to other variables and functions, when the variable is defined. The actual value of the simply expanded variable is the result of expanding the text that you write.

It does not contain any references to other variables; it contains their values as of the time this variable was defined. Good eye. Sign up or log in Sign up using Google. Sign up using Facebook. Sign up using Email and Password. Post as a guest Name. Email Required, but never shown.

The Overflow Blog. Podcast Making Agile work for data science. Stack Gives Back Featured on Meta. New post summary designs on greatest hits now, everywhere else eventually. Linked Related Hot Network Questions. If there is no response to an urgent issue, you can escalate to the general security mailing list for advice.

Development of Make, and GNU in general, is a volunteer effort, and you can contribute. For information, please read How to help GNU. If you'd like to get involved, it's a good idea to join the discussion mailing list see above.

We defend the rights of all software users. There are also other ways to contact the FSF. GNU Make GNU Make is a tool which controls the generation of executables and other non-source files of a program from the program's source files.

Capabilities of Make Make enables the end user to build and install your package without knowing the details of how that is done -- because these details are recorded in the makefile that you supply. Make figures out automatically which files it needs to update, based on which source files have changed.

It also automatically determines the proper order for updating files, in case one non-source file depends on another non-source file. Make is not limited to any particular language. For each non-source file in the program, the makefile specifies the shell commands to compute it. These shell commands can run a compiler to produce an object file, the linker to produce an executable, ar to update a library, or TeX or Makeinfo to format documentation.

Make ignores the returned status on command lines that begin with a dash. For example, who cares if there is no core file? Make echoes the commands, after macro substitution to show you what is happening. Sometimes you might want to turn that off.

People have come to expect certain targets in Makefiles. You should always browse first. However, it is reasonable to expect that the targets all or just make , install, and clean is found. The command is one that ought to work in all cases where we build an executable x out of the source code x.

This implicit rule says how to make x out of x. The rule is implicit because no particular target is mentioned. It can be used in all cases. Another common implicit rule is for the construction of. Make can automatically create a. These rules are built-in the make , and you can take this advantage to shorten your Makefile. If you indicate just the. You do not have to include the command for the compiler. Make uses a special target, named. Similar to how make already knows how to make a.

The first rule allows you to create a. It basically scrambles the file. The second rule is the default rule used by make to create a. There are numerous directives available in various forms. The make program on your system may not support all the directives.

So please check if your make supports the directives we are explaining here. GNU make supports these directives. The ifeq directive begins the conditional, and specifies the condition.

It contains two arguments, separated by a comma and surrounded by parentheses. Variable substitution is performed on both arguments and then they are compared. The lines of the makefile following the ifeq are obeyed if the two arguments match; otherwise they are ignored.